B.E. Bonner, W.J. Llope, E. Platner, H. Themann, and M. Wright
T.W. Bonner Nuclear Laboratory, Rice University
Houston, TX 77251-1892
21-July-1995
A number of the electronic components of the STAR-EMC are very similar to those presently being developed at Rice University for the STAR-CTB, TOF, and MWC sub-systems. We propose to exploit this similarity and cost-effectively design, fabricate, and optimize prototypes of these electronic components of the EMC. The components to be included in the present R&D project are:
* the Cockroft-Walton PMT base,
* the dual-range gated integrator circuit for the PMT signals, and
* the transimpedance amplifier circuit for the BSMD and ESMD signals.
The specifications and other relevant information for each of these components are discussed in turn below. The estimates for the parts and labor costs are listed in the next section. The labor estimates are listed in units of hours. These are costed for engineers, engineer assistants, and laborers at the usual rates used in STAR, which are 435$/day (54.38$/hr), 250$/day (31.25$/hr), and 102$/day (12.75$/hr), respectively.
All of the prototypes below involve PC boards, which will be built by commercial manufacturers. Typically, there is a $250 charge for non-recurring engineering, and a minimum order of $750. We will generally purchase the largest possible number of each PC board resulting in the minimum order, which will be from 2 to ~10 boards for the complexity of circuits developed under the present proposal.
It is thought that the magnetic field strength where the EMC PMTs are situated in STAR is low enough that a modest amount of shielding would be capable of zeroing the magnetic fields near the CW bases. This results in a considerable simplification in the design and a significant reduction in the cost of the EMC CW bases as compared to those for, e.g., the CTB, TOF, and VPD systems, which are already under development at Rice.
The Cockroft-Walton (CW) PMT base is to provide high voltage to ten stage Hamamatsu R580 PMTs or possible Russian equivalents. The input to the device is 5V DC. The maximum output will be ~1700V. The sine-wave oscillator frequency will be 40 KHz. The distribution of high voltages from the anode to the first dynode will be according to the ratio 3:2:2:2:1:...:1:2, as described by Lu et al.1 This implies seventeen CW stages, which provide on the order of ~100V each.
The base must regulate the high voltage output to ~0.1% or better, and be capable of operating in conditions for which light pulses strike the PMT at rates up to 10 MHz. The RF noise emitted by the device shall be minimized. The device must be sturdy, and efficiently packaged to minimize its space requirements. The PMT socket, exterior housing, and cable connections will be attached to each prototype so that it is ready for immediate evaluation.
A breadboard version of the proposed CW for the EMC has already been fabricated and tested. The figure below shows results from bench tests of this circuit. The top trace is the 40 KHz oscillator. The middle trace shows that the breadboard prototype is running at -1700V, with a 2V ripple (lower trace), corresponding to ~0.12% of the set-point. We expect to be able to reduce the ripple to approximately 0.5V (~0.03%) by adding low-pass filters to each stage output.
Scope traces from the bench-tests of the breadboard prototype Cockroft-Walton PMT base for the EMC.
Two (2) prototype CW bases with the final mechanical assembly will be produced first. These will be tested at Rice and ANL under realistic conditions. Any revisions to the design that are necessary will then be performed, and ten (10) CWs of the revised design and final mechanical assembly will then be produced. On the basis of our experience developing the CW bases for other applications in STAR, we do not expect a second revision to be necessary.
The EMC must be capable of measuring EM particle energies over a wide range from those emitted with characteristic temperatures of a few hundred MeV to those emitted and boosted at up to 60 GeV in W and Z decays. Accurate measurements over such a scale will be possible by the digitization of the PMT output from each BEMC and EEMC channel with a dual-range gated integrator circuit.
Single-range integrator+ADC circuits providing 8 bits of digitized charge information from the PMTs of the CTB system have already been built and tested at Rice. For the EMC, the dual-range output will be produced via a two channel charge splitter of 50 input impedance. Each output of the splitter is followed by a gated integrator+ADC combination that is similar to that already developed for the CTB. A photograph of the integrator+ADC circuit developed for the CTB is shown below.
The 8-bit single-range integrator+ADC circuit for the CTB.
At least 13(14) bits of dynamic range in the integrator+ADC circuit for the BEMC(EEMC) are necessary. This will be done using two 10-bit ADCs. The breadboard version will provide 8-bit results for each range.
The final gains and overlap between the two ranges will be determined on the basis of bench and in-beam tests of the various versions of the circuit. A discussion of these issues is included in a recent STAR Note . The proposed circuit has been simulated using the SPICE package. These simulations indicate the basic feasibility of conceptual design of the charge splitter - the currents at the integrating capacitors are in the same ratio as the ratio of resistance's in the charge splitter. In the final versions, it is expected that the splitting to the two ranges will be performed by optimizing both the resistors in the charge splitter and the integrating capacitors.
The evaluation of the prototype integrator+ADC circuits will occur in bench tests at Rice and ANL, and in beam tests using the SPEMC. The construction of a VME read-out board will be necessary for the testing of this circuit at Rice. However, such a VME board is also needed for the testing of the CTB integrator+ADC circuit, so this VME board will be paid from funds allocated to the CTB.
A module of 16 channels of transimpedance amplifier for wire chamber signal processing built by one of us.
Transimpedance amplifier circuits will be used for the first processing of the signals from the wire/strip chambers that are the SMD for the EMC. In STAR, these circuits are attached to the chamber inside EMC stack.
In the prototype circuit(s), two different existing transimpedance amplifier chips will be tested. One of these is commercially available, while the other is being developed at UC-Santa Cruz by Dorfan et al. Eight to sixteen of these amplifiers will be packaged into a single module that can be easily connected to one of the existing SMD prototype chambers for evaluation purposes.
There are a number of important questions and considerations to be investigated using the prototype constructed using the commercial and Dorfan chips, which are
* the dynamic range,
* the noise to saturation at 20 MHz,
* the input and output offset voltages,
* the power dissipation, and
* the output rise-time for inputs with rise-times in the range of 10 to 50 ns.
The Dorfan chip development is already well underway at Rice, as it will be used for the STAR MWC and for the DDC in AGS-E896. Prototypes have been built and tested on the bench and in the AGS test beam. The dynamic range is 10-bits, the noise (~3 mV) to saturation (~3V) is 1/1000, the power dissipation is less than 10 mW, and the output rise-time is adjustable between 3 and 20 ns using an external resistor. The bandwidth is 100(15) MHz for rise times of 3(20) nsec. A comparator is also included.
This part of the present proposal is intended to test basic aspects of the performance of these chips for the existing prototype SMDs. If the present tests imply the feasibility of one of these chips, the effort will focus on making the circuit as space efficient as possible. This scenario is expected to be a considerably more cost effective way to amplify the signals from the ~10000 channels of BSMD and ESMD as compared to chips developed from scratch at STAR institutions.
The table below presents the estimates for the labor and parts costs for the work described above. We are prepared to to begin this work immediately upon receipt of these funds.
Component No. Stage Labor Labor Cost
(hrs) ($/hr) ($, FY96)
CW Base, Version I 2 Design 20 EN.R 1087.5
Board Layout 40 EA.R 1250.0
PC boards 1000.0
Electronic Parts 250.0
Sockets/Hardware 150.0
Fabrication 20 LA.R 255.0
Testing/Evaluation
CW Base, Version II 10 Board Layout 20 EN.R 1087.5
PC boards 1000.0
Parts 1000.0
Fabrication 100 LA.R 1275.0
Testing/Evaluation
Integrator, Breadboard 1 Design 40 EN.R 2175.0
Version
Parts 250.0
Fabrication 40 EN.R 2175.0
Integrator, Version I 2 Design 40 EN.R 2175.0
(w/ ADCs)
Board Layout 80 EA.R 2500.0
PC boards 1000.0
Parts 500.0
Fabrication 60 LA.R 765.0
Testing/Evaluation
Integrator, Version II 2 Design 20 EN.R 1087.5
(w/ADCs)
Board Layout 20 EA.R 625.0
PC boards 1000.0
Parts 500.0
Fabrication 60 LA.R 765.0
Testing Evaluation
Amplifier, Version I 8 Design 40 EN.R 2175.0
chs.
Board 80 LA.R 1020.0
Layout/Fabrication
PC Boards 1000.0
Parts and 750.0
connectors
Testing/Evaluation
TOTALS 680 28817.5